Researchers at Stanford have found a way to improve the performance of next-generation processors by coating copper interconnects with graphene.
The biggest factor influencing the improved performance of processors is transistor scaling, which is the concern of Moore’s law, but there are other factors which become important as silicon transistors shrink.
Transistors communicate using copper interconnects, which have begun to approach their limitations as new semiconductor nodes are brought online.
As engineers pack more transistors into the same area, this increases the density of the interconnects – resulting in increased heat.
The first processors with copper interconnects used 1km of copper wiring per square centimetre, while modern 14nm CPUs contain over 10km of interconnects in the same area.
Copper interconnects are constantly shrinking, becoming thinner and increasing their resistance.
While tantalum nitride trenches are a solution, they are not effective for smaller semiconductor nodes.
Stanford researchers believe coating copper interconnects in graphene will allow progress past the 0.3nm node, while maintaining stability and preventing electromigration.