Yes Im aware this example is not exactly my point.
Lets look at the top end 28ore/56 threads Xeon chip.
https://ark.intel.com/content/www/u...inum-8180-processor-38-5m-cache-2-50-ghz.html
2.5ghz effectively per core, turbo speed is pointless if you use server chips fully utilized so meaningless to look at. Thats 36cores @ 2.5Ghz = 70Ghz.
Then look at the Intel Xeon 10core/20 threads.
https://ark.intel.com/content/www/u...-processor-e5-2690-v2-25m-cache-3-00-ghz.html
Each core base is running at 3ghz. Thats 10 cores @ 3Ghz = 30Ghz
So this is what I mean with each iteration of more cores per chip they are dropping the base core clocks and this removes much of the scaling economics that you are after when utilization more cores per chip.
You get 2.33x times the clock with 2.8x the available cores. Also the available lvl3 cache is not at all proportional with the 28core you get 38.5MB cache vs 25MB on the 10core.
Their next iterations will start to come out at 2Ghz per core or even lower as they have already done with other Xeon chips.