How important is CPU cache?

[Thor]

Especially L2 and L3

Example my current CPU:

Threads 6 threads
L2 cache 6 MB
L2 cache per core 1 MB/core
L3 cache 8 MB
L3 cache per core 1.33 MB/core
Manufacture process 32 nm

The Ryzan I want:

Threads 12 threads
L2 cache 3 MB
L2 cache per core 0.5 MB/core
L3 cache 16 MB
L3 cache per core 2.67 MB/core
Manufacture process 14 nm

 

[milomak]

I'm gonna say it's not really

 

[milomak]

I can't edit on Tapatalk

I have an i7 bought from so long ago. I even stopped overclocking it

 

[Progenix Oj101]

Cache is vitally important but can't be compared across architectures. Any given architecture will benefit from more cache (although there are diminishing returns), but one architecture can be more efficient than another with double the cache.

 

[Chevron]

[video=youtube;8u1hd_7nUaw]https://www.youtube.com/watch?v=8u1hd_7nUaw[/video]

 

[sajunky]

Cache is vitally important but can't be compared across architectures. Any given architecture will benefit from more cache (although there are diminishing returns), but one architecture can be more efficient than another with double the cache.

^This. Just give Ryzan a try.

 

[Thor]

Still waiting for that computer scientist to pop in here and explain to me what it is and how it works.

 

[cguy]

Still waiting for that computer scientist to pop in here and explain to me what it is and how it works.

Too tired. Google!

Simply though, it keeps recently used memory on chip so that it can read or write to it with lower latency, higher bandwidth than main memory (which is usually off chip) and lower power. L1-4 describes how close the cache is to the core (L1 being smallest and fastest, and L3 (and sometimes L4) being the largest and slowest - but still faster than main memory). Different sizes, architecture, policies and coherence models allow various trade offs (bandwidth, latency, die area, core count scalability, etc.) for different applications.

 

[Marius Flash]

And here i thought i knew a little something about IT....... HuH??? All Greek to me

 

[Thor]

Too tired. Google!

Simply though, it keeps recently used memory on chip so that it can read or write to it with lower latency, higher bandwidth than main memory (which is usually off chip) and lower power. L1-4 describes how close the cache is to the core (L1 being smallest and fastest, and L3 (and sometimes L4) being the largest and slowest - but still faster than main memory). Different sizes, architecture, policies and coherence models allow various trade offs (bandwidth, latency, die area, core count scalability, etc.) for different applications.

Perfect. Now it all makes sense.