RISC, why did it never make it to larger Computing systems?

CT_Biker said:
This is why I specifically asked this. I have a pretty old book, Its DOD MIL-STD book(The big red one from the 80s), and it appears that that for all internal DOD systems they used RISC for just about everything, SUN was listed as a provider and IBM of course.
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Of course they did... they didn't have greedy Bill Gates with his pals at Intel in their mix.
 
CT_Biker said:
When you dev for Embedded platforms, what do you actually develop? Links to Git maybe? Or Drop me a PM? I'll be keen to have a look and read some of your code.
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Gadgets... blobs.. the stuff I do for work is in the company repo which is unfortunately not public
 
Also you have to define "larger" computing systems.

The last generation of consoles and those before it were all RISC-based and sold in the millions so would count as fairly large in my view and you have them in most homes.
 
CT_Biker said:
I did notice that a few supercomputers have been built on RISC, CISC doesn't really seem to be efficient when compared to RISC.

Horses for courses I take it?
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For supercomputing, the biggest performance consideration is usually the amount of die area allocated to floating point pipelines. The relatively low area overhead of RISC (vs CISC) on the front-end of the chip is now a marginal consideration (it a huge issue back when there were no floating point pipelines at all). Intel has by far the best floating point density AND single threaded performance I've seen together on a desktop CPU, which is one of the reasons it has dominated that space.

The Summit supercomputer uses GPUs for it's compute density (much higher than CPUs). The NVLINK alternative to PCIE on the Power9's makes Power9 a better choice for many GPU workloads, which is one of the key reasons it was chosen for the Summit CPUs. Power CPUs are pretty meh for CPU performance - they're expensive, have relatively poor FPU performance, and although in terms of IPC, they can be faster than the Intel CPUs, they typically require 4 threads/core to get there.

Trying to cripple GPU computing by not widening the slow PCIE alternative is probably the biggest reason x86 is starting to drop out of supercomputing. The MIC isn't a great alternative to GPUs yet.

IIRC, China's latest supercomputer is a custom RISC core with a ton of compute density on it. Almost like a GPU with a CPU on it - this makes it fast for very parallel code, but running branchy code would be a disaster.

It's also probably worth mentioning that the "CISC" computers these days (basically x86), typically convert to a RISC like microcode at the front-end for internal processing, and much of the newer instruction set extensions are RISC like. Also, "RISC" computers often now have a ton of instructions too, so the lines are getting blurring somewhat.
 
cguy said:
It's also probably worth mentioning that the "CISC" computers these days (basically x86), typically convert to a RISC like microcode at the front-end for internal processing, and much of the newer instruction set extensions are RISC like. Also, "RISC" computers often now have a ton of instructions too, so the lines are getting blurring somewhat.
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Yip, ii was already said:
ponder said:
They did, sort of. The x86 intel and amd cpus moved to risc like cores a long time ago, intel since P6 not sure about amd.
cisc instructions are broken up into smaller parts uops which are executed by the risc cores.
x86 sells and has a huge legacy, can't just move away from that.
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CT_Biker said:
As per thread title, I would like to know why RISC type processors never crossed over to larger computing systems, like servers, laptops and desktop pc's
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RISC isn't well suited for general computing.
 
Swa said:
RISC isn't well suited for general computing.
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I don’t think that is inherent to RISC. Rather x86 was used at the right place at the right time, which created a massive legacy dependency.
 
RISC is typically a load-and-store architecture which basically means everything has to go via CPU registers.
In the old days, with crappy designs this led to inefficiencies.
 
cguy said:
I don’t think that is inherent to RISC. Rather x86 was used at the right place at the right time, which created a massive legacy dependency.
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RISC has to be specifically programmed and compiled for. Instructions have to be serialised without dependencies as it loses much of its advantage when a core is idle. It's also incredibly memory hungry and a lot of the space saving ends up going towards cache and registers. Besides for this extra development a lot of tasks end up still having code that would bog down a true RISC processor. Most implementations of it have extra instructions and circuitry to handle these cases as opposed to being pure RISC based. Most modern systems now are in fact a combination of both as opposed to implementing only one architecture.
 
Swa said:
RISC has to be specifically programmed and compiled for. Instructions have to be serialised without dependencies as it loses much of its advantage when a core is idle. It's also incredibly memory hungry and a lot of the space saving ends up going towards cache and registers. Besides for this extra development a lot of tasks end up still having code that would bog down a true RISC processor. Most implementations of it have extra instructions and circuitry to handle these cases as opposed to being pure RISC based. Most modern systems now are in fact a combination of both as opposed to implementing only one architecture.
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Indeed.. I remember thinking years ago... “man this sucks the 80386 can do a memory to memory copy this stupid thing wants me to go via registers”
 
cguy said:
I don’t think that is inherent to RISC. Rather x86 was used at the right place at the right time, which created a massive legacy dependency.
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It's not something you can get away from. risc & cisc both have their pros & cons.
 
Swa said:
RISC has to be specifically programmed and compiled for.
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This is true for any ISA, no?

Swa said:
Instructions have to be serialised without dependencies as it loses much of its advantage when a core is idle.
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Superscalar Out Of Order execution and RISC are not incompatible.

Swa said:
It's also incredibly memory hungry and a lot of the space saving ends up going towards cache and registers.
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How is it memory hungry? There can be a slightly larger instruction footprint but it’s easily prefetchable. Relative to data today, this is tiny.
 
cguy said:
This is true for any ISA, no?
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More for RISC than for CISC. Performance hinges mostly on the quality of the code and how instructions are rearranged from CISC to RISC. Compilers are thus harder to implement and are more device specific as well as requiring a deeper understanding of the compiler. CISC pretty much doesn't matter as code will execute in the most efficient manner.

cguy said:
Superscalar Out Of Order execution and RISC are not incompatible.
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Maybe not but not what I was really referring to. RISC is most suited to where data can independently be executed in parallel. Where there's dependencies it doesn't function so well.

cguy said:
How is it memory hungry? There can be a slightly larger instruction footprint but it’s easily prefetchable. Relative to data today, this is tiny.
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It requires larger on-die cache as well as memory bus as feeding the instructions require faster memory access.
 
RISC, why did it never make it to larger Computing systems?

It actually did, there is the little thing called ARM, known as Advanced Risc Machines , or originally Acorn Risc Machine, acorns original implementation was for their home computer , it was design to be low power and efficient as it could not exceed 1W due to its plastic substrate.

If you mean the more traditional Risc based implementation, IBM had a huge server market using it and it found its way into last get consoles Xbox 360, PlayStation 3, and Wii all of them ran Risc.

Even modern x64 implimentations are semi Risc.
 
FaSMaN said:
.......

If you mean the more traditional Risc based implementation, IBM had a huge server market using it and it found its way into last get consoles Xbox 360, PlayStation 3, and Wii all of them ran Risc.

Even modern x64 implimentations are semi Risc.
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AIX on the RS/6000,heady old days of computing...

I started my IT career training as an IBM systems engineer in 1990....on AIX and CAD/CAM/CAE software which where being moved and sold to more cost efficient/portable Risc servers/workstations from costly/old System/360 Mainframes running MVS.
 
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